eMMC

eMMC (short for embedded MultiMediaCard) is a form of managed NAND flash that is similar to an SD card (except soldered down). It is a NAND flash die combined with a flash controller inside a single soldered-down BGA package. The controller handles wear-levelling, error correction (ECC) and bad-block management internally, and presents a simple block-addressable interface to the host. This makes eMMC easy to use as memory. From the host’s point of view it behaves much like a small, non-removable hard drive.

It is standardised by JEDEC under the JESD84 series of standards.¹ These standards define not just the electrical protocol but also the physical package (almost always a BGA) and the pinout.

eMMC Is A Soldered-Down SD Card (Almost)

The quickest way to understand eMMC is by comparison to an SD card. Both are managed NAND: NAND flash plus a controller doing the same housekeeping (wear-levelling, ECC, bad-block management). The differences are mostly about packaging and interface:

• eMMC is a soldered-down BGA package, not a removable card. This gives it better shock/vibration resistance and a smaller footprint, at the cost of not being user-replaceable.
• eMMC and SD both descend from the original MMC (MultiMediaCard) standard. SD branched off and added its own features; eMMC kept evolving the embedded side.
• Because the same NAND-management concepts apply, most of what is on the SD Cards page — multi-level cells (SLC/MLC/TLC), pSLC, wear-levelling and TRIM — applies equally to eMMC.

The Interface

eMMC uses a parallel bus consisting of a clock, a bidirectional command line, and a data bus that can be 1, 4 or 8 bits wide. The 8-bit data bus (only available because it is soldered down, not squeezed into a card connector) is one of the key throughput advantages over an SD card.

Over the various revisions of the standard, several speed modes have been added:²

Speed mode	Bus	Clock	Peak throughput	Introduced
Legacy	SDR	$26\unit{MHz}$	~$26\unit{MB/s}$	MMC
High Speed SDR	SDR	$52\unit{MHz}$	~$52\unit{MB/s}$	eMMC 4.x
High Speed DDR	DDR	$52\unit{MHz}$	~$104\unit{MB/s}$	eMMC 4.4
HS200	SDR	$200\unit{MHz}$	~$200\unit{MB/s}$	eMMC 4.5
HS400	DDR	$200\unit{MHz}$	~$400\unit{MB/s}$	eMMC 5.0

HS400 achieves its $400\unit{MB/s}$ by running the 8-bit bus in double-data-rate (DDR) mode at $200\unit{MHz}$. DDR is when data is transferred on both the rising and falling clock edges. This means the worst case fundamental frequency of the data (a repeating pattern of 0101...) is the same as the clock. eMMC 5.1 later added command queuing (CQ), which lets the host issue multiple commands without waiting for each to complete, improving random-access performance.

Tip

The quoted speeds do not account for the overhead of the protocol and the time it takes to either store written data or to retrieve data for returning back to the host. The throughput of actual data seen by the host will be lower than the peak throughput listed in the table.²

I/O is typically run at $1.8\unit{V}$ for the high-speed modes (with $3.3\unit{V}$ supported for legacy compatibility).

Partitions

Unlike a raw flash chip or a simple SD card, an eMMC device presents several distinct hardware-level partitions:

• User data area: the main bulk storage, where the filesystem lives.
• Boot partitions: two small dedicated partitions that a host SoC’s boot ROM can read from directly at power-up, before the main OS is running. This is heavily used in embedded Linux boards.
• RPMB (Replay Protected Memory Block): a small partition with authenticated, replay-protected access, used for storing security-sensitive data such as keys or rollback counters.
• General purpose partitions: up to four optional partitions the host can configure for its own use.

Packaging

eMMC is essentially always a BGA package. Unusually, the eMMC standard specifies the mechanical package and ballout itself (not just the electrical protocol), so a compliant device is a ball grid array by definition. The variation between parts is in ball count and body size rather than package family:

• 153-ball and 169-ball FBGA, both in an $11.5 \times 13\unit{mm}$ body — by far the most common.
• 100-ball FBGA — a smaller footprint used by some parts.
• A handful of other ball counts and pitches appear across vendors, but they are all BGA variants.

You won’t find eMMC in a leaded package (SOIC, TSOP, QFN) or through-hole. The high-speed parallel bus — HS400 runs DDR at $200\unit{MHz}$ on an 8-bit bus — together with the power and ground distribution it needs, makes a ball grid array the only practical choice. This is different from plain SPI/QSPI NOR/NAND flash, which is commonly available in SOIC, WSON and TSOP packages.

Adapter boards that carry a BGA eMMC and break it out to an SD-card edge or a header do exist, but that is a small PCB with an eMMC on it, not a different chip package.

Comparison To Other Storage

	Raw NAND	eMMC	SD Card	UFS
Controller	None (host manages)	On-package	On-card	On-package
Removable	No	No (soldered)	Yes	No (soldered)
Interface	Parallel NAND	Parallel (up to 8-bit)	Parallel (up to 4-bit)	Serial (M-PHY, full-duplex)
Host complexity	High (needs FTL + ECC)	Low	Low	Low
Typical peak speed	Varies	~$400\unit{MB/s}$ (HS400)	~$100\unit{MB/s}$+ (UHS)	$1\unit{GB/s}$+

• Raw NAND is unmanaged — the host processor must run a flash translation layer (FTL) and do its own ECC and wear-levelling in software (e.g. via UBI/UBIFS on Linux). eMMC moves all of that into the package.
• UFS (Universal Flash Storage) is the modern successor to eMMC. Instead of a parallel bus it uses a high-speed serial link (M-PHY) that is full-duplex and supports command queuing natively, reaching much higher throughput. UFS has largely replaced eMMC in high-end phones, while eMMC remains popular in cost-sensitive and embedded designs.

Reliability and Industrial Use

Because eMMC use managed NAND memory, it inherits all of NAND flash’s fundamental wear-out mechanisms. These are the same concerns that people have with using SD cards in industrial applications:

• Limited program/erase (P/E) endurance: each cell can only be erased and rewritten a finite number of times before it wears out. The limit depends heavily on the cell type — SLC lasts far longer than MLC, which lasts far longer than TLC.
• Finite data retention: a written cell slowly leaks its stored charge over time. Retention gets worse at high temperature and as the cell accumulates wear, so a heavily-used device holds data for a much shorter time than a fresh one.
• Read/write disturb and unexpected-power-loss corruption: also NAND-level effects common to all managed-NAND storage.

Just like with an SD card, the on-package controller can mitigate some of these issues with techniques such as wear-levelling, ECC, and bad-block management.

Saying that, eMMC is more attractive for industrial and embedded designs due to it’s robustness and supply-chain control (when compared to SD cards):

• Soldered-down BGA: no friction connector to corrode, wear or vibrate loose. Removable card contacts are a genuine field-failure mode that eMMC eliminates, giving it much better shock and vibration resistance.
• A known, specified part: you solder a specific vendor part number with a published datasheet stating endurance, temperature range and (sometimes) power-loss protection. Commodity SD cards are notorious for silent BOM changes, relabelled parts and undocumented controllers.
• Industrial-grade options: as with SD cards, eMMC is available in pSLC mode and with wide-temperature ratings, trading capacity for greatly improved endurance and retention over consumer TLC. A good example is ATP Electronics’ E700Pi series, an eMMC 5.1 (HS400) part in a 153-ball FBGA that runs 3D NAND in pseudo-SLC mode across 8–64 GB and a $-40$ to $+85\unit{^\circ C}$ industrial temperature range. ATP quotes 2–3× the endurance of a standard eMMC for it.³ The tell-tale sign of pSLC is the reduced usable capacity — because only one bit is stored per cell, the same die yields roughly a third of the density it would as 3D TLC.

So eMMC is generally considered more suitable than a consumer SD card for industrial use, but that comes from mechanical reliability and knowing exactly what part you have. Those you mitigate the same way in both: choose SLC/pSLC, over-provision, use industrial-temperature parts, and minimise unnecessary writes.

One metric used to measure reliability is TBW (terabytes written). This is an indication of how many terabytes of data can be written to the device before it is expected to fail.

Common Uses

eMMC is extremely common in cost-sensitive and space-constrained embedded systems: older and mid-range smartphones and tablets, single-board computers, automotive infotainment, and IoT devices. For example, the BeagleBone uses on-board eMMC pre-loaded with a Linux image, so the board can boot without an SD card inserted.

Examples

Raspberry Pi CM5

The Raspberry Pi Compute Module 5 (CM5) uses eMMC for its main non-volatile storage. The CM5 comes in a number of variants with either 0, 16, 32 or 64 GB of eMMC (the 0 GB version is called the CM5Lite).⁴ The photo below shows a Samsung Electronics KLMAG1JETD 16 GB eMMC 5.1 IC on the bottom side of a CM5 board:

Photo highlighting the eMMC on the bottom-side of a Raspberry Pi Compute Module 5 (CM5). This particular IC is the Samsung Electronics KLMAG1JETD, which is a 16 GB eMMC 5.1 IC. It is cap+able of ~$400\unit{MB/s}$.

ATP E700Pi

The ATP E700Pi is a range of industrial-grade eMMC 5.1 (HS400) devices. They use “3D pseudo SLC” and come in a range of sizes from 8 GB to 64 GB.³ The max. TBW is 1320 TB (compared to 296 TB for their commercial-grade E700Pc with pSLC and 824 TB for their non-pSLC E600Si).⁵ They are packaged in a 153-ball BGA.

Photo of an ATP 128 GB eMMC 5.1 IC in a 153-ball BGA package.³

Footnotes

1. JEDEC. e.MMC [standards page]. Retrieved 2026-07-16, from https://www.jedec.org/standards-documents/technology-focus-areas/flash-memory-ssds-ufs-emmc/e-mmc. ↩

2. Scott Bronstad (2017, Aug 3). Mastering eMMC Device Programming [white paper]. BPM Microsystems. Retrieved 2026-07-17, from https://www.bpmmicro.com/mastering-emmc-device-programming/. ↩ ↩²

3. ATP Electronics (2020, Jul 31). ATP e.MMC v5.1 Embedded Flash Storage Solution [product brief]. Retrieved 2026-07-19, from https://www.atpinc.com/products/industrial-managed-nand-emmc. ↩ ↩² ↩³

4. Raspberry Pi. Raspberry Pi Compute Module 5 [product page]. Retrieved 2026-07-17, from https://www.raspberrypi.com/products/compute-module-5/?variant=cm5-104032. ↩

5. ATP Electronics. Industrial e.MMC [product page]. Retrieved 2026-07-19, from https://www.atpinc.com/products/industrial-managed-nand-emmc. ↩