Flash Memory
Article by:Geoffrey Hunter
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Overview
Flash ICs typically use the SPI communication protocol for communication to the MCU. This includes single lane SPI for slower flash and quad lane (QSPI) for faster flash. Data clock speeds of 80-100MHz are common1.
NOR Flash
Erase times can vary from approx. 50ms per 4KB sector to over 1s for the full chip1.
![The internal block diagram showing the architecture of the MX25V5126F NOR flash IC from Macronix[^macronix-mx25v5126f-nor-flash-ds].](https://blog.mbedded.ninja/electronics/components/memory/flash/_assets/macronix-mx25v5126f-block-diagram.png)
The internal block diagram showing the architecture of the MX25V5126F NOR flash IC from Macronix1.
NAND Flash
References
Macronix International Co. (2020, Sep 3). MX25V5126F - 2.3V-3.6V, 512K-BIT [x 1/x 2] CMOS Serial NOR Flash [datasheet]. Retrieved 2024-02-08, from https://www.macronix.com/Lists/Datasheet/Attachments/8750/MX25V5126F,%202.5V,%20512Kb,%20v1.1.pdf. ↩︎ ↩︎ ↩︎
Authors
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