|Name||Quad-flat No-leads Package|
|Solderability||Surprisingly easy to solder by hand, as long as the pads extend around to the sides of the IC, and you drill a hole to solder the centre pad from the reverse. QFN packages can also be soldered easily with a infrared rework station or the 'frying pan' technique.|
0.40mm pitch QFN packages:
0.50mm pitch QFN packages:
0.65mm pitch QFN packages:
|Height||1mm (max, applies to all QFN packages, includes stand-off). Some a smaller (e.g. the UT/ultra-thin QFN packages).|
The QFN component package is commonly used today for higher pin-count IC’s such as microcontrollers. It is a near chip-scale package, with all the pins being around the perimeter and an optional thermal pad(s) in the center. It is one of the highest pin-density SMD packages without resorting to BGA. Note that there are different pitch footprints within the QFN family! And QFN packages do not have to be square (square is the most common), some rectangular versions exist with a different number of leads on the two sides (they always have the same number of pins on the opposite side).
QFN packages offer benefits over other packages for high-speed circuits, as well as high heat dissipation capabilities. QFN packages are lacking gull-wing leads (like that present on the QFP package), which create noise in high-speed applications.
Texas Instruments recommends rounded pads on the QFN package to prevent solder bridging. Also, stencil windows are recommended for the solder paste on the thermal pad so that a limited amount of solder is added. Too much solder can cause the QFN package to “float” around during the soldering process.
A QFN-like package with pins on only two of the fours sides is a SON package (DFN).
Confusingly, NXP names it’s range of QFN packages with SOT… (e.g, SOT-662-1), a name which is commonly reserved for transitory packages such as the popular SOT-23.
TI recommends a non-solder mask defined (NSMD) pad over a solder mask defined (SMD) pad. This is to produce consistent and reliable solder joints. As a rule-of-thumb, you want solder mask openings that are 0.1-0.14mm larger than the pad size. By default, Altium uses NSMD pads.
Some QFN packages have an exposed metal feature on the underside to indicate pin 1. If this is the case, make sure this area is covered with solder mask to prevent shorting to neighbouring traces. This is an unusual feature, and personally I have not used any QFN packages with this present.
It is recommended to reduce the amount of solder paste applied to the centre pad to prevent the QFN package from floating during reflow. A rule-of-thumb is to have between 50-80% coverage on the center pad (this obviously does not apply to QFN packages with no pad).
It may be necessary to mask or plug vias in the center pad to prevent solder paste being carried through the via and away from the pad during reflow. Small holed vias (such as vias with a hole diameter of 0.3mm or less) do not normally cause a big problem.
There are two singulation methods for QFN packages:
- Punch singulation: This is used on individually-molded QFN packages.
- Saw singulation: This is used on molded array QFN packages.
The main difference between these two singulation methods is the cross-sectional profile. Punch singulation gives a tapered cross-section (larger cross-section at the bottom than the top), while sawn singulation gives a completely square cross-section.
Punch singulated QFN packages are JEDEC compliant.
Volatiles that get trapped underneath the pad during reflow can cause voids to form underneath the component (areas in where the pad is not soldered to the PCB). Another potential cause of voiding is when too much solderpaste is applied to the centre pad, which causes the package to float on the PCB during reflow.
Because the QFN package sits directly on the PCB and has no standoff, they are less resilient to mechanical stresses that say, QFP packages. The amount of PCB board flex must be taken into consideration. Excessive stress can damage a QFN package.
Unique Corner Pins
QFN packages exist in where the corner pins have to be of a different shape to all the others for clearance reasons. The only example of this I have ever seen is the package for the IvenSense MPU-9250 IMU. It is a QFN package with 24 pins in a 3x3x1.0mm size with 6 0.40mm pitch pins on each edge. Because of the high pin density, the outer pins on each edge almost touch each other, and so a different pin shape is used. This also means you use a different pad shape for the package footprint.
Standardization Of Pinout For Logic Functions
JEDEC has a standard on the pinout of QFN packages for logic functions.