QFN Component Package

The QFN component package is commonly used today for higher pin-count ICs such as microcontrollers. It is a near chip-scale package, with all the pins being around the perimeter and an optional thermal pad(s) in the center. It is one of the highest pin-density SMD packages without resorting to BGA. Note that there are different pitch footprints within the QFN family! And QFN packages do not have to be square (square is the most common), some rectangular versions exist with a different number of leads on the two sides (they always have the same number of pins on the opposite side).

QFN packages offer benefits over other packages for high-speed circuits, as well as high heat dissipation capabilities. QFN packages are lacking gull-wing leads (like that present on the QFP package), which create noise in high-speed applications. However because the package is sitting right on the surface of the PCB (or very close to it), they suffer more from mechanical/thermal stress than other SMD packages with larger stand-offs, such as the QFP package.

Texas Instruments recommends rounded pads on the QFN package to prevent solder bridging. Also, stencil windows are recommended for the solder paste on the thermal pad so that a limited amount of solder is added. Too much solder can cause the QFN package to "float" around during the soldering process.

A QFN-like package with pins on only two of the fours sides is a SON package (DFN).

Confusingly, NXP names it’s range of QFN packages with SOT…​ (e.g, SOT-662-1), a name which is commonly reserved for transitory packages such as the popular SOT-23.

TI recommends a non-solder mask defined (NSMD) pad over a solder mask defined (SMD) pad. This is to produce consistent and reliable solder joints. As a rule-of-thumb, you want solder mask openings that are 0.1-0.14mm larger than the pad size. By default, Altium uses NSMD pads.

Some QFN packages have an exposed metal feature on the underside to indicate pin 1. If this is the case, make sure this area is covered with solder mask to prevent shorting to neighbouring traces. This is an unusual feature, and personally I have not used any QFN packages with this present.

It is recommended to reduce the amount of solder paste applied to the centre pad (also called the mechanical pad or thermal pad) to prevent the QFN package from floating during reflow. A rule-of-thumb is to have between 50-80% coverage on the center pad (this obviously does not apply to QFN packages with no pad).

It may be necessary to mask or plug vias in the center pad to prevent solder paste being carried through the via and away from the pad during reflow. Small holed vias (such as vias with a hole diameter of 0.3mm or less) do not normally cause a big problem.

The central pad may not necessarily be electrically connected to anything.

There are two singulation methods for QFN packages:

The main difference between these two singulation methods is the cross-sectional profile. Punch singulation gives a tapered cross-section (larger cross-section at the bottom than the top), while sawn singulation gives a completely square cross-section.

Punch singulated QFN packages are JEDEC compliant.

Volatiles that get trapped underneath the pad during reflow can cause voids to form underneath the component (areas in where the pad is not soldered to the PCB). Another potential cause of voiding is when too much solderpaste is applied to the centre pad, which causes the package to float on the PCB during reflow.

Because the QFN package sits directly on the PCB and has no standoff, they are less resilient to mechanical stresses that package with leads such as QFP packages. The amount of PCB board flex must be taken into consideration. Excessive stress can damage a QFN package.

QFN packages exist in where the corner pins have to be of a different shape to all the others for clearance reasons. The only example of this I have ever seen is the package for the IvenSense MPU-9250 IMU. It is a QFN package with 24 pins in a 3x3x1.0mm size with 6 0.40mm pitch pins on each edge. Because of the high pin density, the outer pins on each edge almost touch each other, and so a different pin shape is used. This also means you use a different pad shape for the package footprint.

Aside from the unique corner pins that QFN packages can have (as explained above), some QFN packages are completely IC specific and do not follow the "standard" at all. One example is the MPM3620 which comes in a "QFN-20" component package (Figure 10) which has changing pitch, different sized pins, bridged pins and internal pins near the bottom center of the package:

MLP is a common package name used for "non-standard" QFN-like packages, an example is shown in Figure 11.

Another great example is ST Microelectronic’s PWD13F60 high-voltage full-bridge with integrated gate driver IC. It comes in a VFQFPN 10x13x1.0mm package which contains a variety of pad shapes and sizes, as shown in the below image:

Want to see the recommended footprint for this IC? See below!

JEDEC has a standard on the pinout of QFN packages for logic functions.

JESD75-5 - JEDEC Standard - QFN Pinouts For Logic Functions

Component packages which have wettable flanks have a step-cut lead frame and tin added to the sidewalls of the package. This allows a side fillet of solder to form more reliably, aiding automatic optical inspection (AOI)[1] (QFN packages already had pad metallization on the side of the package, but no step-cut nor plating, and side-fillet formation was less reliable).

The QFN package is one of the most common packages for a manufacturer to add wettable flanks to. Wettable flanks was largely driven by the need to AOI in the automotive industry but this package feature is now found to be generally useful in a number of industries.

The tin plating of the flank prevents the traditionally exposed copper (a by-product of the sawing singulation of a single QFN package from a "brick") from oxidizing[2].