PROGRAMMING LANGUAGES
VHDL
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Last Modified: |
2-Input AND Gate
entity AND2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end AND2;
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PROGRAMMING LANGUAGES
Date Published: | |
Last Modified: |
entity AND2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end AND2;