Digital Logic

Arguably the simplest logical gate (ignoring a buffer), a NOT gate (a.k.a. inverter) always outputs the opposite (complement) of the input. If the input is TRUE, the output is FALSE. If the input is FALSE, the output is TRUE.

And this gives rise to the simple equation for NOT logic:

An AND gate outputs TRUE only if all it’s inputs are TRUE. AND is also called logical conjunction[5].

The equation for the AND logic may be written in one of the following ways:

An AND gate can be made using basic diode logic as shown in Figure 3.

A NAND gate is just an AND gate but with the output inverted. This is shown in Figure 4 with the bubble at the output of the AND symbol.

A OR gate is TRUE if at least one input is TRUE. This means it is also outputs TRUE if all it’s inputs are TRUE. OR is also called logical disjunction[5].

The OR operation can be expressed in an equation in the following ways:

A NOR gate is just a OR gate but with the output inverted (i.e. what you would get if you connected the output of an OR gate to an inverter). Just like the NAND gate, the NOR is gate is shown in Figure 6 and is just an OR gate symbol with a bubble on the output.

The equation for an NOR gate:

The OR gate be drawn using three equal diameter circles placed on a grid as shown in Figure 7. Segments of the circles perimeters are taken along with the addition of two horizontal line sections to form the classic OR gate shape[4].

A 2-input XOR gate (exclusive OR) only outputs TRUE if one and only one of it’s inputs is also TRUE.

The symbol \(\bigoplus\) is used to represent XOR, as hence XOR can be written in the following ways:

Figure 10 shows a XOR gate made exclusively from NAND gates.

You can also make a XOR gate exclusively from NOR gates, as shown in Figure 11. Note that the structure is similar to the all-NAND gate version of the XOR, but with the additional inverting gate on the output.

Whilst it is intuitive how a AND or OR gate should work with more than 2 inputs, that same cannot be said for a XOR gate. Should the output be TRUE only if exactly one input is TRUE? Should the output be TRUE if at least 1 but not all of the inputs are TRUE? Or should the output be TRUE if one input is TRUE, FALSE for 2 inputs TRUE, TRUE again for 3 inputs TRUE, e.t.c?

XOR gates are used for:

XNOR is an XOR gate but with the output inverted.

Diode logic (DL) is digital logic circuitry made from just diodes and resistors. It is a very simple (if not the simplest) way of constructing logic gates in a circuit. Diode logic is great for getting a basic theoretical understanding of how logic gates are realized, but is rarely used in practise due to fan-out, switching speed issues, and limited gate constructibility (more on this below)!. Also known as diode-resistor logic (DRL).

Before long you’ll be struck with the solemn realization you can’t create a NOT gate (inverter) from pure diode logic (or any gates that require inverting capabilities, such as NAND or NOR gates). This limits you to being only able to make AND or OR gates, and hence it’s usefulness is severely limited. NOT gates are constructable as soon as you add switching elements, such as transistors. Resistor-transistor logic is the extension of diode logic but the addition of transistors.

Resistor-transistor logic (RTL) is one of the most basic families of digital logic (only diode logic beats it in terms of simplicity). It uses resistors and BJTs to build the basic gates required for digital logic. Now days it is completely superseded by logic families such transistor-transistor logic (TTL) and CMOS. However, it serves as a great place to introduces readers on how logic gates are built from discrete components.

Advantages:

Disadvantages:

TODO: Add info here.

The inputs of TTL logic are the emitters of BJTs.

Represented by AC/ACT in part numbers, or HC/HCT for high-speed equivalents. The T in the logic subfamily name signifies the parts have TTL-compatible inputs.

SR (Set-Reset) latches are the most basic form of flip-flop. It is level triggered.

Driving both set and reset high is a forbidden state. A JK latch is just an extension of the SR latch where the circuit is modified to remove the forbidden state \(S = R = 1\) and instead cause the output to toggle.

SN74LS279 is a quad SR latch component by Texas Instruments. Two of the four latches have two set inputs, allowing for either to be active to set the latch (equivalent to an OR gate placed before a normal single set input SR latch).

SR latches can be used to make a switch debounce circuit.

A D flip-flop (where the D either stands for Delay or Data) is a flip-flop which does not propagate the input to the output until a specific state or change in the clock signal. Figure 18 shows the basic symbol for a D-type flip-flop with no preset or clear.

Figure 19 shows the internals of a flip-flop.

You can actually eliminate the need the inverting/NAND gate altogether by connecting the output of the top NAND to the input of the bottom NAND as shown in Figure 20, saving one gate (lower cost/size).

You may have noticed that the output stage of the D-type flip-flop looks familiar — that’s because it’s just an SR latch! Figure 21 highlights the SR latch section of a D-type flip-flop.

D-type flip-flops are used for counters, shift-registers and input synchronization.

Category: Counter Expression Style: Sum of Products No. of Gates: 14 No. of Flip-flops: 3 1-Bit Inputs: 2 + reset 1-Bit Outputs: 3

Tested On:

Downloads: CEDAR Logic Simulator File

The 6-state binary counter is a counter which counts from 000 to 101 in the normal binary fashion before resetting back to 0. The output increments on every rising-edge of the count pulse, and the direction pin (upNDown) determines the count direction (when upNDown = 1, the counter goes from 000 to 101, when upNDown is 0 the counter goes from 101 to 000).

The flip-flop equations expressed as sums of products are:

Category: Counter Expression Style: Sum of Products No. of Gates: 14 No. of Flip-flops: 3 1-Bit Inputs: 2 + reset 1-Bit Outputs: 3

Tested On:

Download: CEDAR Logic Simulator File

The 3-Bit Grey Encoded Counter is a counter that counts from 0 to 7 in binary in a grey encoded fashion. The counter increments on every rising edge of the bit 'count' and the direction bit 'upNDown' determines the direction of counting.

This quadrature detection circuit is built entirely in hardware, and only uses one flip-flop. It is useful for detecting the direction that an encoder that outputs quadrature signals is spinning in. Potential applications include BLDC motor control. This circuit can be built entirely in reconfigurable PSoC on-chip logic.

When the encoder is spinning in one direction, the output will be logic high (1), when it is spinning in the opposite direction, it will be logic low (0).

A simple delay circuit can be made just by chaining DQ flip-flops together in series (the output of one feeds the input of another). For every flip-flop, the signal will be delayed by one clock-cycle (assuming they all share the same clock source).

This can be used to make a simple timer. Obviously, a limitation is that a flip-flop is needed for every clock cycle of delay needed (try that with a 1000 clock cycle delay!). More advanced timers use binary encoding with the flip-flops to achieve a greater number of states for a lower number of flip-flops.