DIGITAL LOGIC
Digital Logic
Date Published:  
Last Modified: 
1. Overview
Digital logic is the study and application of the fundamentals in digital (binary) electronics, e.g. gates, flipflops, state machines.
2. Logic Gates
Logic gate inputs are normally labelled as a single letter, starting with A
(e.g. a three input AND gate would have inputs A
, B
and C
). The output is normally labelled Y
(in other material you may see this labelled X
), unless you are using a flipflop or latch, and the output is labelled Q
.
There are a few different standards used to draw logic gates on schematics:

MILSTD806B (Graphic Symbols For Logic Diagrams): This most commonly used symbols for basic and/or/xor e.t.c gates is captured in this standard. Each gate has a unique shape and are easily distinguished on a large schematic with many gates. NOT logic is shown with a bubble.

IEC 60617 (ANSI/IEEE Std 911984): All the gates are IClike rectangles with symbols inside to denote the function. NOT logic is shown with a flag on the pin rather than a bubble. Not as easy too quickly identify the gate as MILSTD806B, and not as widely used.

DIN 4070024 (Graphical Symbols; Components For Precision Engineering Devices, Especially Clocks): Ever rarer than the MILSTD806B or IEC 60617 symbols, these are rarely seen. The 1976 Edition was released in June 1976. DIN symbols on this page are referenced to https://de.wikipedia.org/wiki/Logikgatter#Typen_von_Logikgattern_und_Symbolik.
This page uses the convention of TRUE
or 1
to represent the logic state true, and FALSE
or 0
to represent the logic state false.
2.1. NOT
Arguably the simplest logical gate (ignoring a buffer), a NOT gate (a.k.a. inverter) always outputs the opposite (complement) of the input. If the input is TRUE
, the output is FALSE
. If the input is FALSE
, the output is TRUE
.
Inputs  Output 

A 
Y 
0 
1 
1 
0 
And this gives rise to the simple equation for NOT logic:
2.2. AND/NAND
An AND gate outputs TRUE
only if all it’s inputs are TRUE
. AND is also called logical conjunction[5].
Inputs  Output  

A 
B 
Y 
0 
0 
0 
0 
1 
0 
1 
0 
0 
1 
1 
1 
The equation for the AND logic may be written in one of the following ways:
An AND gate can be made using basic diode logic as shown in Figure 3.
A NAND gate is just an AND gate but with the output inverted. This is shown in Figure 4 with the bubble at the output of the AND symbol.
Inputs  Output  

A 
B 
Y 
0 
0 
1 
0 
1 
1 
1 
0 
1 
1 
1 
0 
2.3. OR/NOR
A OR gate is TRUE
if at least one input is TRUE
. This means it is also outputs TRUE
if all it’s inputs are TRUE
. OR is also called logical disjunction[5].
Inputs  Output  

A 
B 
Y 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
1 
The OR operation can be expressed in an equation in the following ways:
A NOR gate is just a OR gate but with the output inverted (i.e. what you would get if you connected the output of an OR gate to an inverter). Just like the NAND gate, the NOR is gate is shown in Figure 6 and is just an OR gate symbol with a bubble on the output.
Inputs  Output  

A 
B 
Y 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
0 
The equation for an NOR gate:
The OR gate be drawn using three equal diameter circles placed on a grid as shown in Figure 7. Segments of the circles perimeters are taken along with the addition of two horizontal line sections to form the classic OR gate shape[4].
2.4. XOR
A 2input XOR gate (exclusive OR) only outputs TRUE
if one and only one of it’s inputs is also TRUE
.
Inputs  Output  

A 
B 
Y 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
0 
The only difference in behaviour between an OR and XOR is when both inputs are TRUE . An OR gate outputs a TRUE in this case, whilst and XOR outputs a FALSE .

The symbol \(\bigoplus\) is used to represent XOR, as hence XOR can be written in the following ways:
Figure 10 shows a XOR gate made exclusively from NAND gates.
You can also make a XOR gate exclusively from NOR gates, as shown in Figure 11. Note that the structure is similar to the allNAND gate version of the XOR, but with the additional inverting gate on the output.
Whilst it is intuitive how a AND or OR gate should work with more than 2 inputs, that same cannot be said for a XOR gate. Should the output be TRUE only if exactly one input is TRUE? Should the output be TRUE if at least 1 but not all of the inputs are TRUE? Or should the output be TRUE if one input is TRUE, FALSE for 2 inputs TRUE, TRUE again for 3 inputs TRUE, e.t.c?

Output TRUE only if 1 and only 1 input is TRUE. This is called a onehot detector. However, this is rarely seen in practise.

Output TRUE only if an odd number of inputs are TRUE. This is called a parity generator or modulo2 adder. This is more commonly implemented behaviour for a XOR gate with more than 2 inputs.
XOR gates are used for:

Parity generators: A sequence of XOR gates can calculate the parity of block of data, which is used for simple singlebit error detection in some communication protocols (e.g. optional setting you can enable with UART)[3].

Correlation/sequence detection: XOR gates output
FALSE
if both inputs are the same. This behaviour can be utilized to perform correlation between two bit streams. 
Cryptographic circuits.
XNOR is an XOR gate but with the output inverted.
Inputs  Output  

A 
B 
Y 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
1 
3. What Are Logic Gates Built From?
3.1. Diode Logic (DL)
Diode logic (DL) is digital logic circuitry made from just diodes and resistors. It is a very simple (if not the simplest) way of constructing logic gates in a circuit. Diode logic is great for getting a basic theoretical understanding of how logic gates are realized, but is rarely used in practise due to fanout, switching speed issues, and limited gate constructibility (more on this below)!. Also known as dioderesistor logic (DRL).
Before long you’ll be struck with the solemn realization you can’t create a NOT gate (inverter) from pure diode logic (or any gates that require inverting capabilities, such as NAND or NOR gates). This limits you to being only able to make AND or OR gates, and hence it’s usefulness is severely limited. NOT gates are constructable as soon as you add switching elements, such as transistors. Resistortransistor logic is the extension of diode logic but the addition of transistors.
3.2. ResistorTransistor Logic (RTL)
Resistortransistor logic (RTL) is one of the most basic families of digital logic (only diode logic beats it in terms of simplicity). It uses resistors and BJTs to build the basic gates required for digital logic. Now days it is completely superseded by logic families such transistortransistor logic (TTL) and CMOS. However, it serves as a great place to introduces readers on how logic gates are built from discrete components.
Advantages:

Very basic to create.

Used a minimal amount of transistors (this was important in the early days of IC fabrication as transistors were expensive!)
Disadvantages:

Very limited fanout.

Significant power consumption: When the transistors are switched on.

Weak drive in one direction: Single transistor strongly drives output only in one direction, pullup/down resistor is used in opposite direction.

Poor noise margins.
LOW
, neither transistor is on and the output is pulled HIGH
by \(R_C\). Any HIGH
input will turn on a transistor, which will drive the output LOW
.3.3. DiodeTransistor Logic (DTL)
TODO: Add info here.
3.4. TransistorTransistor Logic (TTL)
The inputs of TTL logic are the emitters of BJTs.
3.5. CMOS
Represented by AC
/ACT
in part numbers, or HC
/HCT
for highspeed equivalents. The T
in the logic subfamily name signifies the parts have TTLcompatible inputs.
3.6. Comparison
Logic Subfamily  Description  Comment 

AC 
CMOS. 

CVSL 
Cascode voltage switch logic. 

HC 
HCT 

Highspeed CMOS with TTLcompatible inputs. 
Only works with a +5V power supply. Interestingly, still slower than original TTL. 
IIL 
Integrated injection logic. 
LS 

Lowpower Schottky. 
PTL 
4. Logic Gate Part Numbers
Texas Instruments introduced the SN74xx
series of logic ICs in the 1960s, using TTL logic. These parts became very popular and many other manufactures began making pincompatible parts. They kept the 74xx
section of the part number to aid identification, and hence the 74xx
is somewhat standardized across the industry.
The 5400 series is the military rated version of the 7400 series. The 4000 series is the newer CMOS alternative to the 7400 TTL logic. However (and which is somewhat confusing), newer 7400 parts can also be made using CMOS logic, for example, the 74HC4051 analogue multiplexer[2]. These parts commonly using the logic subfamily names HC
or HCT
.
Part Number  Description  Num. Units  Input  Output 

74x00 
Quad 2input NAND gate 
4 
Normal 
Pushpull 
74x01 
Quad 2input NAND gate 
4 
Normal 
Opencollector 
74x02 
Quad 2input NOR gate 
4 
Normal 
Pushpull 
74x03 
Quad 2input NAND gate 
4 
Normal 
Opencollector 
74x04 
Hex inverter gate 
6 
Normal 
Pushpull 
74x05 
Hex inverter gate 
6 
Normal 
Opencollector 
74x06 
Hex inverter gate 
6 
Normal 
Opencollector, 30V/40mA 
74x07 
Hex buffer gate 
6 
Normal 
Opencollector, 30V/40mA 
74x08 
Quad 2input AND gate 
4 
Normal 
Pushpull 
74x09 
Quad 2input AND gate 
4 
Normal 
Opencollector 
74x10 
Triple 3input NAND gate 
3 
Normal 
Pushpull 
74x11 
Triple 3input AND gate 
3 
Normal 
Pushpull 
74x12 
Triple 3input NAND gate 
3 
Normal 
Opencollector 
74x13 
Dual 4input NAND gate 
2 
Schmitt trigger 
Pushpull 
74x4051 
Highspeed 8channel analog multiplexer/demultiplexer 
1 
Analog 
Analog 
74x4052 
Dual 4channel analog multiplexer/demultiplexer 
2 
Analog 
Analog 
74x4053 
Triple 2channel analog multiplexer/demultiplexer 
3 
Analog 
Analog 
The x
is a placeholder for the logic subfamily. For example, in 74LSxx
the LS
represent the lowpower Schottky subfamily.
A company specific prefix may be added to the above part numbers depending on the manufacturer.
Prefix  Company 

<none> 
Nexperia, Phillips 
CD 
Texas Instruments 
DM 
National Semiconductor 
ID 
IDT 
M 
STMicroelectronics 
MC 
OnSemi 
MM 
National Semiconductor 
NLV 
OnSemi 
SN 
Texas Instruments 
TC 
Toshiba 
5. FlipFlops
A flipflop (a.k.a. latch, or bistable multivibrator) is a digital circuit which is able to store a single "bit" of information. It has two stable states (representing a digital 1
or 0
), and they can be made to change state by manipulating digital inputs. Hence they are also called bistable multivibrators (two stable states). Flipflops form the basic storage element in sequential logic.
Flipflops can be either leveltriggered (asynchronous, transparent, opaque) or edgetriggered (synchronous, clocked). Sometimes the word _latch_is exclusively used to refer to leveltriggered flipflops whilst flipflop is reserved for edgetriggered ones only[1].
5.1. SR Latches
SR (SetReset) latches are the most basic form of flipflop. It is level triggered.
S  R  \(Q_{next}\)  Action 

0 
0 
Q 
Hold 
0 
1 
0 
Reset 
1 
0 
1 
Set 
1 
1 
X 
Not allowed 
Driving both set and reset high is a forbidden state. A JK latch is just an extension of the SR latch where the circuit is modified to remove the forbidden state \(S = R = 1\) and instead cause the output to toggle.
SN74LS279
is a quad SR latch component by Texas Instruments. Two of the four latches have two set inputs, allowing for either to be active to set the latch (equivalent to an OR gate placed before a normal single set input SR latch).
SR latches can be used to make a switch debounce circuit.
5.1.1. How Does An SR Latch Work?

\(R\) is
HIGH
and \(S\) isLOW
: Since \(R\) is high, the output of the top NOR gate isLOW
. ThisLOW
feeds into the bottom NOR gate, along with \(S\) which is alsoLOW
, thus the output of the bottom NOR gate isHIGH
. ThisHIGH
feeds into the top NOR gate, which will keep the circuit in this defined state, even if \(R\) is then brought LOW. This gives the SR latch it’s memory. 
\(R\) is
LOW
and \(S\) isHIGH
: Because of the symmetry, the same things happens, but in reverse. \(Q\) isHIGH
and \(\bar{Q}\) isLOW
. Again, if \(S\) goes low, the SR latch "remembers" and keeps it’s outputs in the same state.
5.2. D FlipFlops
A D flipflop (where the D either stands for Delay or Data) is a flipflop which does not propagate the input to the output until a specific state or change in the clock signal. Figure 18 shows the basic symbol for a Dtype flipflop with no preset or clear.
Figure 19 shows the internals of a flipflop.
You can actually eliminate the need the inverting/NAND gate altogether by connecting the output of the top NAND to the input of the bottom NAND as shown in Figure 20, saving one gate (lower cost/size).
You may have noticed that the output stage of the Dtype flipflop looks familiar — that’s because it’s just an SR latch! Figure 21 highlights the SR latch section of a Dtype flipflop.
Dtype flipflops are used for counters, shiftregisters and input synchronization.
5.2.1. Triggering
Edgetriggered D flipflops can be either positive or negative edge triggered. Edgetriggered flipflops are shown by a triangle at the clock input, and negative edgetriggered ones have an additional bubble. However, positiveedge triggered is much more common, and standard practice is to make a negative edge triggered flipflop by adding your own inverting gate on the clock signal.
Adding a inverting gate to the clock signal increasing the propagation delay for that clock input, and will have a significant impact on the operation in highspeed designs. 
5.2.2. Flipflop MTBF
where:
\(t_r\) = resolution time (time since clock edge), \(s\)
\(f\) = sampling clock frequency, \(Hz\)
\(a\) = asynchronous event frequency, \(Hz\)
\(\tau\) = flipflop time constant (this is a function of it’s transconductance), \(s\)
\(T_o\) =
Typical values for a flipflop inside an ASIC could be:

\(t_r = 2.3ns\)

\(\tau = 0.31ns\)

\(T_O = 9.6as\)

\(f = 100MHz\)

\(a = 1MHz\)
Which gives \(\rm MTBF = 20.1days\).
5.3. JK Flipflop
6. Karnaugh Maps
Karnaugh maps are a way of simplifying combinational logic, often used before realising a combination equation into a number of gates to reduce the complexity.
7. Logic Simulators
CEDAR Logic Simulator is my personal favourite. Free, easy to use, colours the wires depending on their state, and allows for named nets as well as direct connections.
8. Example Logic Circuits
8.1. 6State Binary Counter
Category: Counter Expression Style: Sum of Products No. of Gates: 14 No. of Flipflops: 3 1Bit Inputs: 2 + reset 1Bit Outputs: 3
Tested On:

Simulation: Yes (CEDAR Logic Simulator)

Hardware: Yes
Downloads: CEDAR Logic Simulator File
The 6state binary counter is a counter which counts from 000 to 101 in the normal binary fashion before resetting back to 0. The output increments on every risingedge of the count pulse, and the direction pin (upNDown) determines the count direction (when upNDown = 1, the counter goes from 000 to 101, when upNDown is 0 the counter goes from 101 to 000).
The flipflop equations expressed as sums of products are:
8.2. 3Bit Grey Encoded Counter
Category: Counter Expression Style: Sum of Products No. of Gates: 14 No. of Flipflops: 3 1Bit Inputs: 2 + reset 1Bit Outputs: 3
Tested On:

Simulation: Yes (CEDAR Logic Simulator)

Hardware: Yes
Download: CEDAR Logic Simulator File
The 3Bit Grey Encoded Counter is a counter that counts from 0 to 7 in binary in a grey encoded fashion. The counter increments on every rising edge of the bit 'count' and the direction bit 'upNDown' determines the direction of counting.
8.3. Quadrature Detection Circuit
This quadrature detection circuit is built entirely in hardware, and only uses one flipflop. It is useful for detecting the direction that an encoder that outputs quadrature signals is spinning in. Potential applications include BLDC motor control. This circuit can be built entirely in reconfigurable PSoC onchip logic.
When the encoder is spinning in one direction, the output will be logic high (1), when it is spinning in the opposite direction, it will be logic low (0).
8.4. Delay Circuit
A simple delay circuit can be made just by chaining DQ flipflops together in series (the output of one feeds the input of another). For every flipflop, the signal will be delayed by one clockcycle (assuming they all share the same clock source).
This can be used to make a simple timer. Obviously, a limitation is that a flipflop is needed for every clock cycle of delay needed (try that with a 1000 clock cycle delay!). More advanced timers use binary encoding with the flipflops to achieve a greater number of states for a lower number of flipflops.
References

[1] ElectronicsForu (2017, Aug 16). Basics and Overview of Flip Flops. Retrieved 20211019, from https://www.electronicsforu.com/technologytrends/learnelectronics/flipfloprsjktd.

[2] Texas Instruments (1997, Nov). CDx4HC405x, CDx4HCT405x HighSpeed CMOS Logic Analog Multiplexers and Demultiplexers (Datasheet). Retrieved 20211020, from https://www.ti.com/lit/ds/symlink/cd74hc4051.pdf.

[3] Maxim Integrated (2020). Glossary Definition For XOR Gate. Retrieved 20211022, from https://www.maximintegrated.com/en/glossary/definitions.mvp/term/XOR%20Gate/gpk/1202.

[4] McAllister, Willy (2021). Digital logic gates. Spinning Numbers. Retrieved 20211024, from https://spinningnumbers.org/a/logicgates.html.

[5] Wikipedia (2005, Aug 20). List of logic symbols. Retrieved 20211025, from https://en.wikipedia.org/wiki/List_of_logic_symbols.