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Memory

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EEPROM

Even though flash is technically a form of EEPROM, the word EEPROM is usually reserved to smaller-memory, read/write/erase 1 byte at-a-time ICs (flash is usually erased in pages and has way more memory).

The cheapest EEPROM on the market is usually available with an I2C, 1-wire (e.g. UNI/O), or SPI-like (e.g. Microwire) interface, in packages such as the SOT-23-6, SOIC-8 and DIP-8.

Example pinout of a EEPROM IC in a SOT-23-6 component package.

Example pinout of a EEPROM IC in a SOT-23-6 component package.

Unique IDs

Some EEPROM chips also come with unique ID’s burnt into memory. The DS28E05 by Maxim Integrated is one such example. It provides a unique 64-bit ID number which can be read back from read-only memory. It also serves as it’s 1-wire address.

The DS28E05 EEPROM I2C, connected to a microcontroller via the 1-wire interface.

The DS28E05 EEPROM I2C, connected to a microcontroller via the 1-wire interface.

Flash

Flash sometimes uses flip-flop style pin naming conventions. The M25P128 is one such example.

The M25P128 flash IC which uses flip-flop style pin naming conventions.

The M25P128 flash IC which uses flip-flop style pin naming conventions.

SD Cards

NAND flash is used as the main memory device inside of SD cards. There is also a memory controller IC (typically a microcontroller) which acts as an intermediary between the flash and the connected device reading/writing to/from the memory .

The TRIM command

The TRIM command is an ATA command which can be sent to an SSD controller by the OS. It is sent from the OS when a file is deleted from the filesystem, and the OS tells the SSD controller which NAND pages have been deleted. If the controller supports TRIM commands, then it will flag the pages for deletion so that the SSD controller can erase/free the pages. This increases the pool of available memory the wear-levelling algorithm can work with, allowing it to work more effectively and increasing the life time of the storage device.

# m     h       dom     mon     dow     command
0       1       *       *       *       ionice -c 3 fstrim -v /

Wear-levelling

Wear leveling is an intrinsic part of the erase pooling functionality of cards in the SanDisk microSD Card Product Family using NAND memory.1

There are two types of wear-levelling, static and global.

A local cached copy of SanDisk Whitepaper: SanDisk Flash Memory Cards Wear Leveling, October 2003.

Multi-level Cells

A multi-level cell is a individual storage element which can hold more than one bit of information.

  1. SLC (Single Level Cell) is the highest grade of NAND flash. Each cell only has one voltage level it is charged to, allowing only 1-bit to be stored per cell. It is very hard to purchase via standard retail outlets. Example.
  2. MLC (Multi Level Cell) has 4 voltage levels per cell, allowing 2 bits of information to be stored. Read speeds are typically lower than SLC because the controller may need to read the cell at two different voltages to help resolve errors2. MLC cards are also marketed for industrial use. The Intel 8087 was one of the first mass-produced ICs to use MLC technology.

  1. https://datasheet.ciiva.com/26837/getdatasheetpartid-335894-26837658.pdf ↩︎

  2. https://en.wikipedia.org/wiki/Multi-level_cell ↩︎


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