nRF52

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Published On:

Mar 3, 2025

Last Updated:

Mar 13, 2025

The nRF52 Series is a family of SoCs by Nordic Semiconductor. Two of their core features are Bluetooth and low-energy operation. They feature a 32-bit ARM Cortex-M4 CPU.

A photo of the nRF52840 SoC IC.¹

The nRF52 series supports the following wireless protocols with it’s RF radio:¹

Bluetooth 5.4
Bluetooth LE
Bluetooth mesh
Thread
Zigbee
802.15.4
ANT
2.4GHz proprietary protocols

The nRF52840 is likely the most popular MCU in the series and is the most advanced variant in terms of features.¹ It has a 64MHz Cortex-M4 CPU with FPU, 1MB flash and 256kB RAM.

The nRF52 series has good support for using the Zephyr framework to develop the firmware, as is officially backed by Nordic Semiconductor. Zephyr provides a RTOS, peripheral drivers and utility API. There are many project examples and guides available for using Zephyr with the nRF52.

GPIO Pins

This is a placeholder for the reference: fig-nrf52-gpio-port-pin-internal-architecture shows the internal architecture of a GPIO pin on the nRF52 series MCU.

The internal architecture of a GPIO pin on the nRF52 series MCU.²

GPIO Drive Strength

The GPIO pins can be configured in two different drive strengths, standard drive and high drive. This is a placeholder for the reference: tbl-nrf52-gpio-pin-current-limits shows the current limits for the GPIO pins when configured in standard drive and high drive. The current limits depend on the supply voltage and are also characterized for different output levels (e.g. 0.4 V is considered the max. for a logic low).

GPIO pin output current limits.²
Parameter	Description	Min	Typ	Max	Unit
$I_{OL,SD}$	Current at $V_{SS}$ +0.4 V, output set low, standard drive, $V_{DD}$ ≥ 1.7	1	2	4	mA
$I_{OL,HDH}$	Current at $V_{SS}$ +0.4 V, output set low, high drive, $V_{DD}$ ≥ 2.7 V	6	10	15	mA
$I_{OL,HDL}$	Current at $V_{SS}$ +0.4 V, output set low, high drive, $V_{DD}$ ≥ 1.7 V	-	3	-	mA
$I_{OH,SD}$	Current at $V_{DD}$ -0.4 V, output set high, standard drive, $V_{DD}$ ≥ 1.7	1	2	4	mA
$I_{OH,HDH}$	Current at $V_{DD}$ -0.4 V, output set high, high drive, $V_{DD}$ ≥ 2.7 V	6	9	14	mA
$I_{OH,HDL}$	Current at $V_{DD}$ -0.4 V, output set high, high drive, $V_{DD}$ ≥ 1.7 V	-	3	-	mA

When using the Zephyr framework for writing firmware, Zephyr provides nRF specific GPIO flags for controlling the drive strength. The drive strength is individually configurable for both a logic low and a logic high output. This is done with the following macros, which set the upper 8 bits of the gpio_dt_flags_t struct:³

NRF_GPIO_DRIVE_S0: Logic low, standard drive
NRF_GPIO_DRIVE_H0: Logic low, high drive
NRF_GPIO_DRIVE_S1: Logic high, standard drive
NRF_GPIO_DRIVE_H1: Logic high, high drive

These flags are defined in the Zephyr repo under zephyr/include/zephyr/dt-bindings/gpio/nordic-nrf-gpio.h. For example, the following code is used to configure a GPIO pin with high drive in both directions using the gpio_pin_configure_dt() function:

#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h> // Needed for the NRF_GPIO_DRIVE_H0H1 macro

// Update the PATH according to your .dts file(s)
const struct gpio_dt_spec l_myGpio = GPIO_DT_SPEC_GET(DT_PATH(outputs, myGpio), gpios);

int main() {
    // Configure the GPIO pin as output, defaulting to low, with high drive in both directions. Other flags can be ORed in here too as needed.
    int intRc = gpio_pin_configure_dt(&l_myGpio, GPIO_OUTPUT_INACTIVE | NRF_GPIO_DRIVE_H0H1);
    __ASSERT_NO_MSG(intRc == 0);
}

Successive Approximation ADC (SAADC)

The nRF52 series MCUs have a 12-bit successive approximation ADC peripheral called SAADC. This peripheral can be used to convert analogue voltages on the AIN0-AIN7 pins to digital values. It can be used in single ended mode or differential mode. This is a placeholder for the reference: fig-saadc-internal-block-diagram-nrf52 shows the internal block diagram of the SAADC peripheral.

The internal block diagram of the SAADC peripheral on the nRF52 series MCU.²

The accumulator in the SAADC can be to find the average of multiple samples (oversampling). This is used to improve the SNR of the data. Oversampling can be configured with the OVERSAMPLE register. 2^OVERSAMPLE samples are averaged together before one result is written to memory. The DONE event is triggered for each input sample, and the RESULTDONE event is triggered once per averaged sample written to memory.

SAADC uses EasyDMA to write conversion results to RAM memory.

The SAADC peripheral cannot generate events when the converted value crosses a threshold. If you need this functionality, look at using the comparator peripheral (COMP) instead. The same analog input pin cannot be used for both SAADC and COMP peripherals at the same time.

Comparator (COMP)

The nRF52 series MCUs have a comparator peripheral called COMP. Much like discrete analogue comparator ICs, this peripheral can be used to compare one input voltage (VIN+) against another input voltage (VIN-), and can generate events (e.g. raise an interrupt) depending on the result (whether it is higher or lower than the other). VIN+ can be any of the analog input pins AIN0-AIN7. VIN- can be any of the analog input pins (differential mode) or from VREF, which in turn can be derived from VDD, AIN0-AIN7, or internal 1.2V, 1.8V or 2.4V references. It’s internal block diagram is shown in This is a placeholder for the reference: fig-comparator-diagram-nrf52.

The internal architecture of the comparator peripheral on the nRF52 series MCU.²

Events can be generated from:²

UP on VIN- > VIN+
DOWN on VIN- < VIN+
CROSS on VIN- crossing VIN+
READY event when core and internal reference are ready.

These built-in events make comparator great for simple analogue change detection. The ADC peripheral (SAADC) does not have these events, so if using an ADC instead you would need to continuously poll the ADC result and compare it using CPU time (which would both be higher power and a potential waste of CPU processing time).

The comparator peripheral has configurable hysteresis to prevent false events due to noise on the inputs. In differential mode, the hysteresis is set through the HYST register and can either be set to disabled or a fixed 50mV. In single ended mode, hysteresis can be set using VUP and VDOWN thresholds. The up and down thresholds in single ended mode offer much more flexibility than the HYST register available in differential mode.

The comparator peripheral have different speed modes, which also determine the power consumption. The speed modes are set using the MODE register. The different modes are:

Low-power mode
Normal mode
High-speed mode

Nordic Semiconductor. Products / nRF52840 [product page]. Retrieved 2025-03-03, from https://www.nordicsemi.com/Products/nRF52840. ↩ ↩² ↩³
Nordic Semiconductor (2024, Oct 1). nRF52840 - Product Specification - v1.11 [datasheet]. Retrieved 2025-03-03, from https://docs.nordicsemi.com/bundle/ps_nrf52840/page/keyfeatures_html5.html. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶
Zephyr Project (2025, Mar 3). Device Driver APIs > GPIO Driver APIs > nRF-specific GPIO Flags [documentation]. Retrieved 2025-03-03, from https://docs.zephyrproject.org/apidoc/latest/group__gpio__interface__nrf.html. ↩