Digital Logic


Digital logic is the study and application of the fundamentals in digital (binary) electronics, e.g. gates, flip-flops, state machines.

Child Pages

Logic Gates
ContentsOverviewD Flip-FlopsImportant ParametersTriggering Overview When sourcing logic IC’s, note that the standard prefix used by many manufactures is “74”. Logic gate inputs are normally labelled as a single letter, starting with A (e.g. a three input AND gate would have inputs A, B and C). The output is normally labelled Y, unless you are using … Continue reading Logic Gates
Metastability And Synchronisation
ContentsFlip-flop MTBF Flip-flop MTBF $$ {\rm MTBF}(t_r) = \frac{e^{ \frac{t_r}{\tau} } } {T_O fa}$$ where: \( t_r \) = resolution time (time since clock edge), \( s \) \( f \) = sampling clock frequency, \(Hz\) \( a \) = asynchronous event frequency, \(Hz\) \( \tau \) = flip-flop time constant (this is a funciton … Continue reading Metastability And Synchronisation

Karnaugh Maps

Karnaugh maps are a way of simplifing combinational logic, often used before realising a combination equation into a number of gates to reduce the complexity.

Logic Simulators

CEDAR Logic Simulator is my personal favourite. Free, easy to use, colours the wires depending on their state, and allows for named nets as well as direct connections.

Example Logic Circuits

6-State Binary Counter

Category: Counter
Expression Style: Sum of Products
No. of Gates: 14
No. of Flip-flops:  3
1-Bit Inputs: 2 + reset
1-Bit Outputs: 3
Tested On:


The 6-state binary counter is a counter which counts from 000 to 101 in the normal binary fashion before resetting back to 0. The output increments on every rising-edge of the count pulse, and the direction pin (upNDown) determines the count direction (when upNDown = 1, the counter goes from 000 to 101, when upNDown is 0 the counter goes from 101 to 000).

The flip-flop equations expressed as sums of products are:

Q_2 = \bar{Q_2}.\bar{Q_1}.\bar{Q_0}.\bar{y} + \bar{Q_2}.Q_1.Q_0.y + Q_2.\bar{Q_1}.Q_0.\bar{y} + Q_2.\bar{Q_1}.\bar{Q_0}.y \\ \\
Q_1 = \bar{Q_2}.\bar{Q_1}.Q_0.y + \bar{Q_2}.Q_1.\bar{Q_0}.y + \bar{Q_2}.Q_1.Q_0.\bar{y} + Q_2.\bar{Q_1}.\bar{Q_0}.\bar{y} \\ \\
Q_0 = \bar{Q_2}.\bar{Q_0} + Q_2.\bar{Q_1}.\bar{Q_0} \\ \\
Schematic of a six state binary counter.

3-Bit Grey Encoded Counter

Category: Counter
Expression Style: Sum of Products
No. of Gates: 14
No. of Flip-flops: 3
1-Bit Inputs: 2 + reset
1-Bit Outputs: 3
Tested On:

The 3-Bit Grey Encoded Counter is a counter that counts from 0 to 7 in binary in a grey encoded fashion. The counter increments on every rising edge of the bit ‘count’ and the direction bit ‘upNDown’ determines the direction of counting.

Schematic of a three-bit Grey encoded binary counter.

Quadrature Detection Circuit

This quadrature detection circuit is built entirely in hardware, and only uses one flip-flop. It is useful for detecting the direction that an encoder that outputs quadrature signals is spinning in. Potential applications include BLDC motor control. This circuit can be built entirely in reconfigurable PSoC on-chip logic.

When the encoder is spinning in one direction, the output will be logic high (1), when it is spinning in the opposite direction, it will be logic low (0).

A simple quadrature phase detection circuit using a D flip-flop.

Delay Circuit

A simple delay circuit can be made just by chaining DQ flip-flops together in series (the output of one feeds the input of another). For every flip-flop, the signal will be delayed by one clock-cycle (assuming they all share the same clock source).

A simple four clock-cycle delay element made from four DQ flip-flops. This can be used as a simple timer.

This can be used to make a simple timer. Obviously, a limitation is that a flip-flop is needed for every clock cycle of delay needed (try that with a 1000 clock cycle delay!). More advanced timers use binary encoding with the flip-flops to achieve a greater number of states for a lower number of flip-flops.