GENERAL PROGRAMMING
Makefiles
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Contents
Overview
Makefiles are a way of making a “one touch” build solution for source code. They are a type of file used by the GNU command make. They take multiple file inputs, do some part or all of the code build process, and produce output(s). They are commonly used to create executables, object files, or libraries (combined object files) from source code. They come in particularly useful when dealing with large projects.
They are textfiles that are stored with the filename “Makefile” (or “makefile”), with no file extension (do not call it makefile.txt!). The capital M version is recommended because it persists at the top of the directory, along with other important files like the README.
Makefiles are most commonly used to compile code for Linux environments, but also works in Windows, and for embedded systems.
Unlike most other programming/scripting languages, Makefiles are white-space sensitive. This can be annoying! Take care when coping makefile code from the internet, the clipboard can easily convert tabs into spaces and cause the makefile code to break.
Make can be then used by “higher-level” build programs, such as the Autoconfig and Automake tools .
The Simplest Possible Makefile
The simplest possible makefile is (please correct me if I’m wrong):
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If in Linux, opening a terminal, typing make and pressing enter while in the same directory as this makefile will compile a file called main.c with the GCC compiler and produce the output executable file main.o
.
The primary three things a Makefile consists of are targets, prerequisites, and recipes. The above code contains two of these, main.o
, which is the target, and gcc -o main.o main.c
, which is the recipe. Make interprets this code as saying “You make main.o by running the command gcc -o main.o main.c in the terminal.”. Note that all recipes are run in the terminal, and each new recipe (which is on a new line), is run in a different instance of the terminal.
There is a tab infront of the recipe gcc …. . This is important! All recipes must be proceeded by a tab.
If no parameters are passed in when you call make, the first rule in the makefile will be run.
Adding Variables
Make supports variables that are defined before they are used in a rule. The value of the variable is substituted to replace the constant at run-time, similar to the C preprocessor.
You assign a value to a variable in the following ways:
VARIABLE = VALUE | Normal assignment of a variable. Any other variables within in it are recursively expanded when the variable is used, not when it is declared. This is the same bahvaviour you would expect from a variable declared in C. |
VARIABLE := VALUE | Any other variables within in it are expanded on declaration (instanlty). This is similar behaviour to if you declared a const variable in C++. |
VARIABLE ?= VALUE | This sets the variable only if it doesn't have a value already. If the variable hasn't already been set, the actual calculation of the value will be deferred intil when it is used (like VARIBLE = VALUE. |
VARIABLE += VALUE | This appends VALUE to the value that VARIBALE already has. Determining when to calculate the variable follows how it was initially set (i.e. with = or :=). |
There are common names that most people use for variables, which are shown below.
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The && is so that make will only be called if cd is successful. If this wasn’t there and cd was not successful, make would be called in the wrong directory.
Debugging
Make prints out some debug information to the standard output when it is run. If you want more debugging functionality, try Remake, which is a patched version of GNU Make with better error reporting, and trace execution/debugging capability.
More Reading
For a comprehensive reading, checkout the GNU ‘make’ manual.
Authors

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