Home / Programming / Programming Languages / VHDL VHDLArticle by:Geoffrey HunterDate Published:May 5, 2013Last Modified:May 5, 20132-Input AND Gate1 2 3 4 entity AND2 is port (in1, in2: in std_logic; out1: out std_logic); end AND2; AuthorsGeoffrey HunterDude making stuff. Twitter GitHubThis work is licensed under a Creative Commons Attribution 4.0 International License .TagsPlease enable JavaScript to view the comments powered by Disqus.comments powered by Disqus2-Input AND Gate